The present invention relates to the structure and fabrication of semiconductor devices, and more particularly to the structure and fabrication of diodes and field effect transistors of integrated circuits.
Diodes are frequently used in integrated circuits such as those provided in complementary metal oxide semiconductor (CMOS) circuits which utilize n-type and p-type field effect transistors, i.e., NFETs and PFETs, as basic circuit elements. Diodes are used for numerous applications including sensing temperature and for providing precision voltage references such as bandgap reference circuits. In many applications, diodes are required to have an ideality which is close to unity.
In many processing sequences used to fabricate transistors in CMOS technology, pre-amorphization implants (PAI) are utilized prior to performing implants to form extension and/or source/drain regions. The PAI can be performed using a variety of different species, germanium (Ge), silicon (Si) and xenon (Xe) being examples. PAIs create end-of-range (EOR) defects in the silicon which can be beneficial in forming FETs in certain applications, especially for countering floating body effects in silicon-on-insulator (SOI) transistor technology. However, EOR defects are incompatible with retaining high diode ideality. As a result, CMOS processing sequences need a specialized process flow which is simultaneously required to produce both optimized FETs and high diode ideality.
One example of a diode according to the prior art is illustrated in a sectional view in FIG. 1. The diode shown in FIG. 1 is suitable for fabrication on a CMOS integrated circuit. The diode is fabricated by steps in which PFETs and NFETs of the chip are formed simultaneously. Processing steps that are used to form the NFETs and the PFETs of the integrated circuit are also utilized to form the diode. This results in the diodes having structures similar to gate conductors of FETs, such structures appearing to incorporate half of a gate conductor of a PFET and half of a gate conductor of an NFET. On one half of the gate conductor structure 14, the NFET half, thin spacers 16 are disposed. As particularly shown in FIG. 1, the location of the anode 10 is determined by thick spacers 12 which are disposed on sidewalls of the PFET half of the gate conductor structure 14. The thick spacers of the diode are provided in regions where a p-type dopant is implanted (the anode). This results because the same design level is used to form p-doped regions of PFETs and PFETs require thick spacers for design reasons.